1. Field of the Invention
The invention relates generally to power management in computer systems. More specifically, the invention relates to a method and apparatus for dynamically controlling the processing speed of a central processing unit (CPU).
2. Background Art
Recent advances in semiconductor technology have led to the development of high-performance CPUs. These high-performance CPUs operate at high frequencies and usually have high power dissipation. In general, the power dissipated, or consumed, by a CPU is related to the number of instructions the CPU executes per clock cycle. The higher the number of instructions executed per clock cycle, the higher the power consumed by the CPU. In addition, the higher the amount of power consumed by the CPU, the higher the heat dissipated by the CPU. To prevent excessive rise in the temperature of the CPU, the power consumption of the CPU is usually controlled. Traditional techniques prevent excessive rise in the temperature of the CPU by decreasing the CPU clock rate when the CPU stops significant processing or is waiting for an event to take place. Another technique for preventing excessive rise in the temperature of the CPU involves using sensors to monitor the temperature of the CPU and then decreasing the CPU clock rate when the temperature reaches or exceeds a predetermined threshold. U.S. Pat. No. 6,081,901 issued to Dewa et al. describes a power control system that allows a user to accelerate or decelerate a CPU""s processing speed through an interface such as a hot key or a button on a display screen.
In one aspect, the invention relates to a power dissipation control mechanism for a CPU which comprises a power estimation circuit and a speed controller. The power estimation circuit estimates the power dissipation of instructions executed by the CPU during a selected time interval, and the speed controller adjusts the speed of the CPU in response to the estimated power dissipation produced by the power estimation circuit.
In another aspect, the invention relates to a method for controlling the power dissipation of a CPU. The method comprises estimating the power dissipation of instructions executed by the CPU during a selected time interval. During normal operation of the CPU, the method further includes checking to see if the estimated power dissipation is greater than a first predetermined value. If the estimated power dissipation is greater than the first predetermined value, the method further includes reducing the speed of the CPU. The speed can be adjusted either by decreasing the CPU clock rate or by stalling the CPU. While the CPU is operating at reduced speed, the method further includes checking to see if the estimated power dissipation is smaller than a second predetermined value. If the estimated power dissipation is smaller than the second predetermined value, the method further includes increasing the speed of the CPU.
In another aspect, the invention relates to a microprocessor which comprises a CPU, a power estimation circuit, and a speed controller. The power estimation circuit estimates the power dissipation of instructions executed by the CPU during a selected time interval, and the speed controller adjusts the speed of the CPU in response to the estimated power dissipation produced by the power estimation circuit.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.